Integrated circuit chips and in particular CMOS (Complementary-Metal-Oxide-Semiconductor) integrated circuit chips fabricated with bulk silicon techniques can exhibit a phenomenon known as latch-up if triggered by a high enough voltage level. During latch-up the integrated circuit is short circuited, with the result that the integrated circuit draws excessive current and power from the power supply, usually resulting in thermal destruction of the integrated circuit chip.
Examination of the CMOS integrated circuit structure generally reveals that a vertical p-n-p bipolar transistor is formed by the p.sup.+ (more heavily doped p region) drain/source regions of the p-channel MOSFET (metal-oxide-semiconductor field-effect-transistor), the n-tub and the p-substrate. Furthermore, there is a lateral n-p-n transistor consisting of the n-tub, p-substrate and n.sup.30 (more heavily doped n region) drain/source regions of the n-channel MOSFET. The structure is often complicated further by the inclusion of input protection diodes (n.sup.+ p to the substrate and p.sup.+ n to the n-well), and p.sup.+ contacts to the substrate and n.sup.30 contacts to the tub. The presence of these bipolar transistors constitute a potential n-p-n-p device that can latch-up if the right conditions are met.
Basically a necessary condition for latch-up to exist is that the product of the n-p-n and p-n-p transistor gains exceed unity. In addition, the end junctions of the structure must somehow become forward biased. This condition is not satisfied in normal operation, but it could occur during a transient or in a high radiation environment. The final condition is that the VDD supply and the input circuit be capable of supplying the holding current of the p-n-p-n device. The p-n-p-n structure can then go into positive feedback and behave like a short circuit. The signal feeds upon itself and grows exponentially until it turns into an uncontrollably large current short-circuit path.
The more compact the CMOS structure becomes in order to pack more components economically on a chip, the smaller the components become and the closer the junctions are, resulting in increased latch-up problems.
Methods of reducing or eliminating the latch-up tendency include the use of lightly doped epitaxial layer over heavily doped substrate and guard rings around the devices. Of these methods, the heavily doped substrate method has proven to be at least partially successful in preventing latch-up in CMOS integrated circuitry.
This method includes the use of a thick heavily doped starting substrate, as for example a p.sup.+ material, onto which is grown by an epitaxial method a thin layer of lightly doped material, as for example a p.sup.- material. The thick heavily doped starting substrate effectively shorts out the above described parasitic junction, preventing the development of a forward bias across a pair of junctions.
The epitaxial layer is created by a well-known technique. Basically the heavily doped starting substrate material is placed in a furnace. Through a gaseous chemical process, molecules are deposited on the starting material in order to form the epitaxial layer which is an extension of the crystal structure of the starting substrate material.
The disadvantages associated with this type of solution are as follows. First normally the growth of epitaxial layers is not accomplished in-house by a semiconductor manufacturer. This is considered a specialty operation which is one of the most difficult steps in the CMOS fabrication process. As such, this fabrication involves greater expense and extra logistical difficulties.
The second disadvantage is that it is relatively difficult to control the thickness of the deposited epitaxial layer. This is due to the fact that furnace temperature and time controls, as well as several other controls, are not precise enough. Thus as the trend toward making more compact CMOS structures with thinner and thinner layers continues, such techniques will not prove practicable.
The third disadvantage is that when the chip is subjected to subsequent fabrication steps, such as the driving in of p-wells or n-wells, the heavily doped substrate will diffuse toward the surface of the chip. In order to counteract this, the highly doped starting material is positioned further away from the surface, which is counterproductive to producing compact CMOS structures. However even so, the diffusion process evens out the previously sharp demarcation between the epitaxial layer and the highly doped area. It is to be understood that as the sharpness between the heavily doped starting material and the lightly doped epitaxial material is reduced, there is an accompanying degradation in anti-latch-up performance.
The present invention is directed to overcoming the above disadvantages.